Current mode logic (CML) is a logic form well known for use in high-speed digital circuits. Its most popular type emitter-coupled logic (ECL) is frequently integrated into complex logic forms using series-gating techniques in which the differential amplifiers of the basic ECL gates are arranged in a current-switch "tree" configuration. As many as three levels of series gating have been used in commercial devices.
A more recent form of CML is emitter-function logic (EFL) and it has been shown to possess distinct power-display (PXD) advantages over ECL for a number of logic configurations. For example, the basic EFL gate forms an efficient noninverting gate and when used in a series-gated configuration with one level ECL, forms an efficient D-latch and 2:1 multiplexer.
However, such a one-level EFL gate, either alone or in combination with a one-level ECL gate, forms essentially noninverting gates and so lacks versatility; and although the combination can be configured to provide both true and complement variables, such configuration adds wiring and collector-junction capacitances to a critical timing mode, thus degrading performance without adding substantially to the logic flexibility of the gate.
Logic flexibility is particularly important in gate array chips. Bipolar gate array chips typically contain a repetitive arrangement, or iteration, of a large number of identical TTL or ECL logic gates at successive sites in a common silicon chip with the individual sites effectively separated from one another although sharing a common substrate. Desired logic functions are realized by the later discretionary interconnection of these individual gates.
The usefulness of a gate array is determined by the versatility of the logic gates included therein.